Technical Reports

CSL-TR-00-809   Pipelineable Division Unit , Albert Liddicoat and and Michael J. Flynn, September 2000. (992kB)

CSL-TR-00-808   Parallel Computation of the Square and Cube Function , Albert Liddicoat and and Michael J. Flynn, August 2000. (330kB)

CSL-TR-00-790 Reciprocal Approximation Theory with Table Compensation. Albert Liddicoat and M. J. Flynn. January 2000.

CSL-TR-99-786 High Speed Interconnect Schemes for Pipelined FPGA. Hyuk-Jun Lee and M. J. Flynn. August 1999.

CSL-TR-99-783 Optimum ILP for Superscalar and VLIW Processors. Patrick Hung and M. J. Flynn. August 1999.

CSL-TR-99-784 The M-log-Fraction Transform (MFT) for Computer Arithmetic. O. Mencer, M. J. Flynn, M. Morf, July 1999.

CSL-TR-99-780 Coarse Grain Carry Architecture for FPGA. Hyuk-Jun Lee and Michael Flynn. February 1999.

CSL-TR-99-776 Novel Checkpointing Algorithm for Fault Tolerance on a Tightly-Coupled Multiprocessor. Dwight Sunada, David Glasco and Michael Flynn. January 1999.

CSL-TR-98-772 Designing a Partitionable Multiplier. Hyuk-Jun Lee and Michael Flynn. October 1998.

CSL-TR-98-756 Hardware-assisted Algorithms for Checkpoints. Dwight Sunada, David Glasco and Michael Flynn. July 1998.

CSL-TR-98-755 ABSS v2.0: a SPARC Simulator. Dwight Sunada, David Glasco and Michael Flynn. April 1998.

CSL-TR-97-745 Selection of Recent Advances in Computer Architecture. Oskar Mencer, December 1997. (177 kB)

CSL-TR-97-737 Stochastic Congestion Model for VLSI Systems. Patrick Hung and Michael J. Flynn, October 1997. (1465 kB)

CSL-TR-97-718   Fault Tolerance: Methods of Rollback Recovery. Dwight Sunada, D. Glasco and M. Flynn, March 1997. (523 kB)

CSL-TR-96-711   Design Issues in High Performance Floating Point Arithmetic Units, Stuart F. Oberman, December 1996. (450 kB) [pdf]

CSL-TR-96-707   Reducing Cache Miss Rates Using Prediction Caches, James E. Bennett and Michael J. Flynn, October 1996. (90 kB)

CSL-TR-95-706   Optimum Placement and Routing of Multiplier Partial Product Trees, Hesham Al-Twaijry and Michael Flynn, September 1996. (80 kB)

CSL-TR-96-700   Fast IEEE Rounding for Division by Functional Iteration, Stuart F. Oberman and Michael J. Flynn, July 1996. (71 kB)

CSL-TR-96-698   Technology Scaling Effects on Multipliers, H. Al-Twaijry and M. J. Flynn, July 1996. (108kB)

CSL-TR-96-689   A Variable Latency Pipelined Floating-Point Adder, Stuart F. Oberman and Michael J. Flynn, February 1996. (93 kB)

CSL-TR-96-687   Latency Tolerance for Dynamic Processors, James E. Bennett and Michael J. Flynn, January 1996. (68 kB)

CSL-TR-95-684   Performance/Area Tradeoffs in Booth Multipliers, Hesham Al-Twaijry and Michael Flynn, November 1995. (352 kB)

CSL-TR-95-683   A Comparison of Hardware Prefetching Techniques for Multimedia Benchmarks, Daniel F. Zucker, Michael J. Flynn, and Ruby B. Lee, December 1995. (209 kB)

CSL-TR-95-679   Measuring the Complexity of SRT Tables, Stuart F. Oberman and Michael J. Flynn, November 1995. (112 kB)

CSL-TR-95-675   An Analysis of Division Algorithms and Implementations, Stuart F. Oberman and Michael J. Flynn, July 1995. (216 kB)

CSL-TR-95-672   Delay Models for CMOS Circuits, Grant McFarland and Michael Flynn, June 1995. (232 kB)

CSL-TR-95-670   Design and Analysis of Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors, David B. Glasco, June 1995. (1.5 MB)

CSL-TR-95-668   Architecture Evaluator's Work Bench and its Application to Microprocessor Floating Point Units, Steve Fu, Nhon Quach and Michael Flynn, June 1995. (312 kB)

CSL-TR-95-666   On Division and Reciprocal Caches, Stuart F. Oberman and Michael J. Flynn, April 1995. (112 kB)

CSL-TR-95-662   Limits of Scaling MOSFETs, Grant McFarland and Michael Flynn, November 1995. (187 kB)

CSL-TR-95-661   Performance Factors for Superscalar Processors, James E. Bennett and Michael J. Flynn, February 1995. (96 kB)

CSL-TR-95-658   RYO: A Versatile Instruction Instrumentation Tool for PA-RISC, Daniel F. Zucker and Alan H. Karp, January 1995. (108 kB)

CSL-TR-94-657   Instruction Level Parallel Processors - A New Architectural Model for Simulation and Analysis, Kevin W. Rudd, December 1994. (105 kB)

CSL-TR-94-654   Multipliers and Datapaths, Hesham Al-Twaijry and Michael Flynn, December 1994. (98 kB)

CSL-TR-94-647   Design Issues in Floating-Point Division, Stuart F. Oberman and Michael J. Flynn, December 1994. (95 kB)

CSL-TR-94-639   Two Case Studies in Latency Tolerant Architectures, James E. Bennett and Michael J. Flynn, October 1994. (93 kB)

CSL-TR-94-635   A Performance/Area Workbench for Cache Memory Design, Osamu Okuzawa and Michael J. Flynn, August 1994. (55 kB)

CSL-TR-94-630   Expansion Caches for Superscalar Processors, John D. Johnson, June 1994. (70 kB)

CSL-TR-94-616   Reuse of High Precision Arithmetic Hardware to Perform Multiple Concurrent Low Precision Calculations, Daniel F. Zucker and Ruby B. Lee, April 1994. (112 kB)

CSL-TR-94-615   Wave Pipelining of High Performance CMOS Static RAM, Kevin J. Nowka and Michael J. Flynn, January 1994. (216 kB)

CSL-TR-94-613   Design and Validation of Update-Based Cache Coherence Protocols, David B. Glasco, Bruce A. Delagi, and Michael J. Flynn, March 1994. (240 kB)

CSL-TR-94-612   Write Grouping for Update-Based Cache Coherence Protocols, David B. Glasco, Bruce A. Delagi, and Michael J. Flynn, March 1994. (94 kB)

CSL-TR-94-611   The Impact of Cache Coherence Protocols on Systems Using Fine-Grain Data Synchronization, David B. Glasco, Bruce A. Delagi, and Michael J. Flynn, March 1994. (120 kB)

CSL-TR-94-605   Area and Performance Analysis of Processor Configurations with Scaling of Technology, Steve Fu and Michael Flynn, March 1994. (168 kB)

CSL-TR-94-600   Environmental Limits on the Performance of CMOS Wave-Pipelined Circuits , Kevin J. Nowka and Michael J. Flynn, January 1994. (136 kB)

CSL-TR-94-599   The Design and Implementation of a High-Performance Floating-Point Divider, Stuart Oberman, Nhon Quach, and Michael Flynn, January 1994. (112 kB)

CSL-TR-93-596   Models of Communication Latency in Shared Memory Multiprocessors, Gregory T. Byrd, December 1993. (88 kB)

CSL-TR-93-588   Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors , David B. Glasco, Bruce A. Delagi, and Michael J. Flynn, November 1993. (128 kB)

CSL-TR-93-579   Comparative Studies of Pipelined Circuits, Fabian Klass and Michael Flynn, July 1993. (240 kB)

CSL-TR-93-576   A Scalable Computer Architecture for Lattice Gas Simulations, Fung Fung Lee, August 1993. (887 kB) Tech-report pdf (1608kB)

CSL-TR-93-574   Specialized Caches to Improve Data Access Performance, Brian K. Bray, May 1993. (792 kB)

CSL-TR-93-572   Subnanosecond Arithmetic, M. J. Flynn, G. DeMicheli, R. F. Pease, and B. Wooley, May 1993. (128 kB)

CSL-TR-93-571   Research in Computer Architecture, M. J. Flynn, January 1993. (216 kB)

CSL-TR-92-553   Branch Prediction Using Large Self History, John D. Johnson, December 1992. (207 kB)

CSL-TR-92-549   Balancing Circuits for Wave Pipelining, Fabian Klass, October 1992. (115 kB)

CSL-TR-92-530   Sparse Adaptive Memory, Brian Flachs, M. J. Flynn, June 1992. (408 kB)

CSL-TR-92-528   Binary Multiplication Using Partially Redundant Multiples, Gary Bewick, Michael J. Flynn, June 1992. (472 kB)

CSL-TR-91-501   Design and Implementation of the SNAP Floating-Point Adder, Nhon Quach and Michael Flynn, December 1991. (136 kB)

CSL-TR-91-459   On Fast IEEE Rounding, Nhon Quach, Naofumi Takagi, and Michael Flynn, January 1991. (136 kB)

CSL-TR-90-443   A Queuing Analysis for Disk Array Systems, Mikito Ogata and Michael J. Flynn, August 1990. (236 kB)

CSL-TR-90-442   An Improved Algorithm for High-Speed Floating-Point Addition, Nhon T. Quach and Michael J. Flynn, August 1990. (136 kB)