Technical Reports

• Stochastic Congestion Model for VLSI Systems. Patrick Hung and Michael J. Flynn. (CSL-TR-97-737)
• Fault Tolerance: Methods of Rollback Recovery. Dwight Sunada, David Glasco and Michael Flynn. (CSL-TR-97-718)
• Reducing Cache Miss Rates Using Prediction Caches. James E. Bennett and Michael J. Flynn. (CSL-TR-96-707)
• Optimum Placement and Routing of Multiplier Partial Product Trees. Hesham Al-Twaijry and Michael J. Flynn. (CSL-TR-96-706)
• Fast IEEE Rounding for Division by Functional Iteration. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-96-700)
• Technology Scaling Effects on Multipliers. Hesham Al-Twaijry and Michael J. Flynn. (CSL-TR-96-698)
• Delay Balancing of Wave Pipelined Multiplier Counter Trees Using Pass Transistor Multiplexers. Hidechika Kishigami, Kevin J. Nowka and Michael J. Flynn. (CSL-TR-96-692)
• A Variable Latency Pipelined Floating-Point Adder. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-96-689)
• Latency Tolerance for Dynamic Processors. James E. Bennett and Michael J. Flynn. (CSL-TR-96-687)
• Performance/Area Tradeoffs in Booth Multipliers. Hesham Al-Twaijry and Michael J. Flynn. (CSL-TR-95-684)
• A Comparison of Hardware Prefetching Techniques For Multimedia Benchmarks. Daniel F. Zucker, Michael J. Flynn and Ruby B. Lee. (CSL-TR-95-683)
• Measuring the Complexity of SRT Tables. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-95-679)
• An Analysis of Division Algorithms and Implementations. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-95-675)
• Delay Models for CMOS Circuits. Grant McFarland and Michael Flynn. (CSL-TR-95-672)
• Architecture Evaluator's Work Bench and its Application to Microprocessor Floating Point Units. Steve Fu, Nhon Quach and Michael Flynn. (CSL-TR-95-668)
• On Division and Reciprocal Caches. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-95-666)
• Limits of Scaling MOSFETs. Grant McFarland and Michael J. Flynn. (CSL-TR-95-662)
• Performance Factors for Superscalar Processors. James E. Bennett and Michael J. Flynn. (CSL-TR-95-661)
• Multipliers and Datapaths. Hesham Al-Twaijry and Michael J. Flynn. (CSL-TR-94-654)
• Design Issues in Floating-Point Division. Stuart F. Oberman and Michael J. Flynn. (CSL-TR-94-647)
• Two Case Studies in Latency Tolerant Architectures. James E. Bennett and Michael J. Flynn. (CSL-TR-94-639)
• A Performance/Area Workbench for Cache Memory Design. Osamu Okuzawa and Michael J. Flynn. (CSL-TR-94-635)
• Communication Mechanisms in Shared Memory Multiprocessors. Gregory T. Byrd, Bruce A. Delagi and Michael J. Flynn. (CSL-TR-94-623)
• Design and Validation of Update-Based Cache Coherence Protocols. David B. Glasco, Bruce A. Delagi and Michael J. Flynn. (CSL-TR-94-613)
• Performance and Area Analysis of Processor Configurations with Scaling of Technology. Steve Fu and Michael J. Flynn. (CSL-TR-94-605)
• Environmental Limits on the Performance of CMOS Wave-Pipelined Circuits. Kevin J. Nowka and Michael J. Flynn. (CSL-TR-94-600)
• The Design and Implementation of a High-Performance Floating-Point Divider. Stuart Oberman, Nhon Quach and Michael J. Flynn. (CSL-TR-94-599)
• Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors. David B. Glasco, Bruce A. Delagi and Michael J. Flynn. (CSL-TR-93-588)
• Comparative Studies of Pipelined Circuits. Fabian Klass and Michael J. Flynn. (CSL-TR-93-579)
• Fetch Caches. Brian K. Bray and Michael J. Flynn. (CSL-TR-93-561)
• Using a Floating-Point Multiplier's Internals for High-Radix Division and Square Root. Eric M. Schwarz and Michael J. Flynn. (CSL-TR-93-554)
• Binary multiplication Using Partially Redundant Multiples. Gary Bewick and Michael J. Flynn. (CSL-TR-92-528)
• Paging Performance with Page Coloring. William L. Lynch and Michael J. Flynn. (CSL-TR-91-492)
• Suggestions for Implementing a Fast IEEE Multiply-Add-Fused Instruction. Nhon Quach and Michael Flynn. (CSL-TR-91-483)
• Subnanosecond Arithmetic (Second Report). Michael J. Flynn, Giovanni DeMicheli, Robert Dutton, R. Fabian Pease and Bruce Wooley. (CSL-TR-91-481)
• Strategies for Branch Target Buffers. Brian K. Bray and M. J. Flynn. (CSL-TR-91-480)
• Writes Caches as an Alternative to Write Buffers. Brian K. Bray and Michael J. Flynn. (CSL-TR-91-470)
• Leading One Detection--Implementation, Generalization, and Application. Nhon Quach and Michael J. Flynn. (CSL-TR-91-463)
• On FAST IEEE Rounding. Nhon Quach, Naofumi Takagi and Michael J. Flynn. (CSL-TR-91-459)
• Page Allocation to Reduce Access Time of Physical Caches. Brian K. Bray, William L. Lynch and Michael J. Flynn. (CSL-TR-90-454)
• A Queuing Analysis for Disk Array Systems. Mikito Ogata and Michael J. Flynn. (CSL-TR-90-443)
• An Improved Algorithm for High-Speed Floating-Point Addition. Nhon T. Quach and Michael J. Flynn. (CSL-TR-90-442)
• Sub-Nanosecond Arithmetic. Michael J. Flynn, Giovanni DeMicheli, Robert Dutton, Bruce Wooley and R. Fabian Pease. (CSL-TR-90-428)
• A VLSI Architecture for the FCHC Isometric Lattice Gas Model. Fung F. Lee, Michael J. Flynn and Martin Morf. (CSL-TR-90-426)
• High-Speed Addition in CMOS. Nhon T. Quach and Michael J. Flynn. (CSL-TR-90-415)
• An Area-Utility Model for On-Chip Memories and its Application. Johannes M. Mulder, Nhon T. Quach and Michael J. Flynn. (CSL-TR-90-413)
• Branch Strategies: Modeling and Optimization. Pradeep K. Dubey and Michael J. Flynn. (CSL-TR-90-411)
• Sparse, Distributed Memory Prototype: Principles and Operation. Michael J. Flynn, Pentti Kanerva and Neal Bhadkamkar. (CSL-TR-89-400)
• The Relative Effects of Optimization on Instruction Architecture Performance. K. J. Cuderman and M. J. Flynn. (CSL-TR-89-398)
• Sparse Distributed Memory Prototype: Address Module Hardware Guide. M. J. Flynn, R. Zeidman and E. Lochner. (CSL-TR-88-373)
• Sparse, Distributed Memory Prototype: Principles of Operation. Michael J. Flynn, Pentti Kanerva, Bahram Ahanin, Paul A. Flaherty, Philip Hickey and Neal A. Bhadkamkar. (CSL-TR-87-338)
• Design of Testbed and Emulation Tools. Michael J. Flynn and Stephen Lundstrom. (CSL-TR-87-337)
• Design of Testbed and Emulation Tools. Stephen F. Lundstrom and Michael J. Flynn. (CSL-TR-86-309)
• A Theory of Interpretive Architectures: Some Notes on DEL Design and a FORTRAN Case Study. Lee Hoevel and Michael J. Flynn. (CSL-TR-79-171)
• Interpretive Architectures: A Theory of Ideal Language Machines. Michael J. Flynn and Lee Hoevel. (CSL-TR-79-170)
• The Structure of Directly Executed Languages: A New Theory of Interpretive System Design. Lee W. Hoevel and Michael J. Flynn. (CSL-TR-77-130)
• The Stanford Emulation Laboratory. Michael J. Flynn, Lee W. Hoevel and Charles J. Neuhauser. (CSL-TR-76-118)