This year we have developed tools for studying the effect of I/O storage systems on overall systems performance.
The PAWB is a set of tools to aid in the research of multiple instruction, multiple data (MIMD) multiprocessors. It consists of the AWB tools with extensions to support a Parallel C front end, multiprocessor trace generation, and a communications interconnect/memory hierarchy description. The scope of the PAWB is to do research into the class of multiprocessors with 2-64 processors, high speed 32-bit processing elements, and exploiting large grain parallelism.
The PAWB simulates the execution of a multiprocessor by creating a separate process for each processor on a host uniprocessor. Currently, context switches between processors use the scheduler of the host machine. This will be improved to use a scheduler that will switch processor simulation at the end of each basic block or shared memory reference of the executing program.
The Parallel Architects Workbench has been revised over the last year to produce a new version of the PAWB (version 2.0). The new PAWB consists of a new configurable simulator that uses the same traces as the previous version, and an Architecture Description file. Features of the new simulator include: