A number of different simulation techniques can be used to study computer architectures. These vary from analytical models to register level descriptions of the proposed architecture. The PAWB simulates behavioral models of each component. Behavioral models better predict the performance of the system then the analytical models, while taking less time to design and simulate then full register transfer level descriptions. Because of the complex nature of Parallel Architectures, the cache simulators used in the AWB had to be expanded to include the finite state machines necessary for cache coherence protocols.