Cache Design Tools

The Cache Design Tools are based on research by Steve Fu. The results provided by the tool follow a more accurate model than the one presented in the book: Computer Architecture, by Prof. M. Flynn.

Caution: We have received complaints that this tool does not give the optimum design in some cases. We are in the process of testing and validating the tool.

First level cache specification :

Technology :

Feature Size in microns : f =

Last update : 10/20/2001

The cache is way set associative.
Cache Size in KBytes:
Line Size in Bytes :
Memory Bus Transfer Unit[Bytes]:
# of Read/Write Ports:
Write Hit Policy: Write Through Write Back
Cell Type: 6T Cell 4T Cell
ISA: R/M R+M L/S
Quantum Length:
Cache Type: Instructions Data Unified
Level of Multiprogramming