Terminology
N-way Set Associativity:
For a review of set associativity see standard computer
architecture textbooks.
Typical values are 1=Direct Mapped,2^x,# of Cachelines=Fully
Associative.
Miss Predictor : supported values are 1,2,4 and 8
Cache Size:
Cache Size is the amount of data that can be stored in the cache.
This does not include tags or control bits. Typically Cache Size is 2^x.
The reason is that this way it is possible to represent all the positions
in the cache with a binary address.
Miss Predictor:supported sizes are 1K - 256K
Cache Line Size:
This is the number of bytes per line.
This value is sometimes also referred to as block size.
Thus the number of lines per cache is simply CacheSize/LineSize.
Miss Predictor:supported values are powers of 2 : 4 - 128
(for associativity of 8) and 16,32,64 (for associativity of 1,2,4)
Number of Ports:
The number of Ports to the cache influences the Area and Cycle Time.
Typical values are 1 to 4.
Memory Bus Transfer Unit:
The cache line consists of smaller parts which are basic units for
transfers from and to memory. This value can also be as the width of
one bank. All the basic units that are at the same position in the
line, form 1 bank. Some designs allow concurrent access of multiple
units iff they are on different banks, otherwise the cache signals a
bank conflict and stalls execution.
Write Hit Policies:
The tradeoff here is if each write hit should access memory (Write
Through) or we Write Back to memory only when a dirty line gets replaced.
Cell Types:
There are multiple ways to design a static (and therefore fast) memory
cell that can store 1 bit of information. The Area estimation tool has
the option of 6 transistors per cell (most common) and 4
transistors. 4 transistor cells take less area but are very unreliable
thus the design is more complex. There most real designs use 6
transistor cells.
Feature Size:
In our case the feature is a transistor and typical values in
microns range from 0.1 to 10. The current state of technology
allows 0.35 microns.
Instruction Set Architecture
The baseline architecture is a R/M machine. The code density
differences affects the miss rate for both the Unified and
Instruction cache.
Level of Multiprogramming
A model based on Markov Chains derived from Haikala's
work is used to model a multiprogramming environment.
The levels supported are 1 - 10. With multiprogramming, the cache is not
flushed between context switches so that when the process is scheduled
once again, some lines may still remain in cache. A key parameter that
needs to be taken into account when adjusting cache miss
rates with multiprogramming level is Quantum Length.
Quantum Length:
Quantum size is the average number of memory references
executed prior to context switch to another process. The quantum sizes
supported are 100,1000,10000,20000, and 100000. For
multiprogramming level of one, the program is assumed to
run to completion and no quantum size adjustment is necessary.
Cache Type:
Different baseline data is used depending on the cache type.
Cache type supported are Unified cache, Instruction cache,
and Data cache.
Values for Cycle Time:
It is sufficient to examine cycle times from T/Sopt to 2*T/Sopt in order to
find the cycle time with the best performance
S:Number of stages corresponding to cycle time
For every cycle time you have to examine the table of events (or
unsplitable units) and figure out how many stages you need for a specific
cycle time.
created by
Oskar Mencer.
Comments, ideas and suggestions :
oskar@leland.stanford.edu
Last update : 7/2/1996