Ordinary pipeline systems operate at a frequency that corresponds to the maximum logic path delay between any two stages. Theoretically, it is possible to increase this frequency by an amount of time equal to the minimum path delay that might occur in the worst-case stage.
In SNAP research, we have shown that it is possible to use CAD tools to automatically increase the minimum or the fast paths to a point where the minimum path logic acts as a significant part of the storage system. We have shown that clocking ECL circuits at 2-1/2 to 3 times the maximum propagation delay is feasible. In a bipolar (ECL) experiment, Wong [P27] showed that the path of a multiplier that had a worst-case path delay of about 10 nanoseconds could be safely clocked at a 4-nanosecond rate. In further research using a CMOS multiplier, Klass [P3] has designed a 6-times improvement in clock rate, resulting in a 600 MHz integer multiplication (see Figure 1).
Figure 1: A wave pipelined multiplier in CMOS (0.8 cycles). Figure shows repetition rate, latency is about 9ns, upper and lower parts show different data patterns.