hos_publish.bib

@ARTICLE{fahmy1995,
  AUTHOR = {Hossam A. H. Fahmy},
  TITLE = {Design and Implementation of {AHD-2494}, a 24-bit {RISC} 
          Processor on a {VLSI} Chip},
  JOURNAL = {`looking.forward' the {IEEE} Computer Society's Student 
          Newsletter},
  YEAR = {1995},
  NOTE = {(fall issue)},
  PS = {publish/look1995.ps.gz},
  PDF = {publish/look1995.pdf}
}

@ARTICLE{fahmy1997,
  AUTHOR = {Hossam A. H. Fahmy and Khaled Ismail},
  TITLE = {Analysis of a Single-electron Decimal Adder},
  JOURNAL = {Applied Physics Letters},
  YEAR = {1997},
  MONTH = MAY,
  VOLUME = {70},
  PAGES = {2613--2615},
  PS = {publish/apl1997.ps.gz},
  PDF = {publish/apl.pdf}
}

@MASTERSTHESIS{fahmyMSc,
  AUTHOR = {Hossam A. H. Fahmy},
  TITLE = {{N}ovel {D}igital {S}tructures {U}tilizing {S}ingle {E}lectron 
          {D}evices},
  SCHOOL = {{D}epartment of {E}lectronics and {E}lectrical 
          {C}ommunications, {C}airo {U}niversity, {E}gypt},
  YEAR = {1997},
  MONTH = MAY,
  PS = {publish/mscthesis.ps.gz},
  PDF = {publish/mscthesis.pdf}
}

@INPROCEEDINGS{fahmy1999_1,
  AUTHOR = {Hossam A. H. Fahmy and Martin Morf and Richard Kiehl},
  TITLE = {Potential Functionality of Multi-valued Tunneling Phase Logic 
          Devices},
  BOOKTITLE = {European Conference on Circuit Theory and Design, Stresa, 
            Italy,  Session {S10-II}},
  YEAR = {1999},
  MONTH = AUG,
  PS = {publish/ecctd1999.ps.gz},
  PDF = {publish/ecctd1999.pdf}
}

@INPROCEEDINGS{hung99,
  AUTHOR = {Patrick Hung and Hossam A. H. Fahmy and Oscar Mencer and
          Michael J. Flynn},
  TITLE = {Fast division algorithm with a small lookup table},
  BOOKTITLE = {Thirty-Third Asilomar Conference on Signals, Systems, and
          Computers, Asilomar, California, {USA}},
  YEAR = {1999},
  MONTH = OCT,
  VOLUME = {2},
  PAGES = {1465--1468},
  PS = {publish/asilomar1999.ps.gz},
  PDF = {publish/asilomar1999.pdf}
}

@INPROCEEDINGS{fahmy1999_2,
  AUTHOR = {Hossam A. H. Fahmy and Richard Kiehl},
  TITLE = {Complete Logic Family Using Tunneling-Phase-Logic Devices},
  BOOKTITLE = {The 11th International Conference on Microelectronics, 
            {ICM} 99, Kuwait},
  YEAR = {1999},
  MONTH = NOV,
  PS = {publish/icm1999.ps.gz},
  PDF = {publish/icm1999.pdf}
}

@INPROCEEDINGS{fahmy01,
  AUTHOR = {Hossam A. H. Fahmy and Albert A. Liddicoat and Michael J. 
          Flynn},
  TITLE = {Improving the Effectiveness of Floating Point Arithmetic},
  BOOKTITLE = {Thirty-Fifth Asilomar Conference on Signals, Systems, and
          Computers, Asilomar, California, {USA}},
  YEAR = {2001},
  MONTH = NOV,
  VOLUME = {1},
  PAGES = {875--879},
  PS = {publish/asilomar2001.ps.gz},
  PDF = {publish/asilomar2001.pdf}
}

@UNPUBLISHED{fahmy_tech01,
  AUTHOR = {Hossam Fahmy and Michael Flynn},
  TITLE = {Leading Digit Detection for Floating Point adders using 
          Signed Digit numbers},
  NOTE = {Not yet published.}
}

@INPROCEEDINGS{fahmy02,
  AUTHOR = {Hossam A. H. Fahmy and Albert A. Liddicoat and Michael J. 
          Flynn},
  TITLE = {Parametric time delay modeling for floating point units},
  BOOKTITLE = {The International Symposium on Optical Science and Technology,
   SPIE's 47th annual meeting (Arithmetic session), Seattle, 
   Washington, USA},
  YEAR = {2002},
  MONTH = JUL,
  PS = {publish/spie2002.ps.gz},
  PDF = {publish/spie2002.pdf}
}

@INPROCEEDINGS{fahmy2003_1,
  AUTHOR = {Hossam Aly Hassan Fahmy and Michael J. Flynn},
  TITLE = {The Case For a Redundant Format in Floating Point Arithmetic},
  BOOKTITLE = {Proceedings of the 16th {IEEE} Symposium on Computer
            Arithmetic, Santiago de Compostela, {S}pain},
  YEAR = {2003},
  MONTH = JUN,
  PS = {publish/arith2003.ps.gz},
  PDF = {publish/arith2003.pdf}
}

@PHDTHESIS{fahmyPhD,
  AUTHOR = {Hossam A. H. Fahmy},
  TITLE = {{A} {R}edundant {D}igit {F}loating {P}oint {S}ystem},
  SCHOOL = {{E}lectrical {E}ngineering {D}epartment, {S}tanford 
          {U}niversity, {USA}},
  YEAR = {2003},
  MONTH = JUN,
  PS = {publish/phdthesis.ps.gz},
  PDF = {publish/phdthesis.pdf}
}

@INPROCEEDINGS{fahmy2003_2,
  AUTHOR = {Hossam A. H. Fahmy and Michael J. Flynn},
  TITLE = {Rounding in Redundant Digit Floating Point Systems},
  BOOKTITLE = {{The International Symposium on Optical Science and Technology,
   SPIE's 48th annual meeting (Arithmetic session), San Diego, 
   California, USA}},
  YEAR = {2003},
  MONTH = AUG,
  PS = {publish/spie2003.ps.gz},
  PDF = {publish/spie2003.pdf}
}

@INPROCEEDINGS{fahmy2004,
  AUTHOR = {Hossam A. H. Fahmy and Michael J. Flynn},
  TITLE = {An adder for a redundant digit arithmetic unit},
  BOOKTITLE = {{COOL Chips VII, Yokohama, Japan}},
  YEAR = {2004},
  MONTH = APR,
  PS = {publish/cool2004.ps.gz},
  PDF = {publish/cool2004.pdf}
}

@INPROCEEDINGS{fahmy2005_1,
  AUTHOR = {Yajuan He and Chip-Hong Chang and Jiangmin Gu and Hossam A. H. 
Fahmy},
  TITLE = {A Novel Covalent Redundant Binary Booth Encoder},
  BOOKTITLE = {{The IEEE International Symposium on Circuits and Systems, 
(ISCAS), Kobe, Japan}},
  YEAR = {2005},
  MONTH = MAY,
  PAGE = {69--72},
  ISBN = {0-7803-8834-8},
  PS = {publish/iscas2005.ps.gz},
  PDF = {publish/iscas2005.pdf},
  ABSTRACT = {The benefit of high radix Booth encoders in reducing the 
number of partial products in fast multipliers has been hampered by the 
complexity of generating the hard multiples. The use of redundant 
binary (RB) Booth encoder can overcome this problem and avoid the error 
compensation vector but at the cost of doubling the number of RB 
partial products. This paper presents a novel covalent RB Booth encoder 
to generate a compound RB partial product from two adjacent Booth 
encoded digits. The new encoder fully exploits the characteristics of 
Booth encoded numbers to restore the effective partial product 
reduction rate of RB Booth encoder while maintaining the simplicity of 
hard multiple generators and eliminating the constant correction 
vector. A legitimate comparison on an $8 \times 8$-bit RB multiplier 
prototype shows that the multiplier constructed with our proposed Booth 
encoder consumes lower power and computes faster than those with the 
normal binary and redundant binary Booth encoders.}
}

@INPROCEEDINGS{fahmy2005_2,
  AUTHOR = {Sherif Tawfik and Hossam A. H. Fahmy},
  TITLE = {Error analysis of a powering method and a novel square root 
          algorithm},
  BOOKTITLE = {{The 17th IMACS World Congress Scientific Computation, 
            Applied Mathematics and Simulation, Paris, France}},
  YEAR = {2005},
  MONTH = JUL,
  PS = {publish/imacs2005.ps.gz},
  PDF = {publish/imacs2005.pdf},
  ABSTRACT = {This paper presents a complete error analysis for a novel
square root hardware implementation. The analysis includes the powering
method used for the initial approximation and the higher order
Newton-Raphson square root iterations. Both theoretical and algorithmic
error analysis are presented and compared. The algorithmic analysis
provides a more accurate error estimate which reduces the size of the
memory required in the initial approximation stage to less than half its
original size. }
}

@INPROCEEDINGS{fahmy:2006:atm,
  AUTHOR = {Sherif A. Tawfik and Hossam A. H. Fahmy},
  TITLE = {Algorithmic Truncation of MiniMax Polynomial Coefficients},
  BOOKTITLE = {{The IEEE International Symposium on Circuits and Systems, 
(ISCAS), Kos, Greece}},
  YEAR = {2006},
  MONTH = MAY,
  PAGE = {--},
  ISBN = {---},
  PS = {publish/iscas2006.ps.gz},
  PDF = {publish/iscas2006.pdf},
  ABSTRACT = {Elementary and high-level functions can be computed
in hardware using polynomial approximation techniques.
There are many techniques in the literature to calculate the
coefficients of such polynomials. Remez algorithm [1] provides
the optimal polynomial in the Chebyshev sense that is minimizing
the maximum error (minimax approximation).
This paper presents an algorithm for truncating the coefficients
of the minimax polynomials obtained from Remez algorithm
using an algorithmic method. A gain of 3 and 4 bits of accuracy
over the direct rounding is reported.
Muller [2] addressed the same problem but his algorithm is
applicable for the second order polynomials only. This paper
presents an algorithm that is applicable for any order.}
}

@INPROCEEDINGS{fahmy:2006:tqc,
  AUTHOR = {Hossam A. H. Fahmy},
  TITLE = {{Typesetting the Qur'an and its specific challenges to the \TeX\
family}},
  BOOKTITLE = {{Euro{\TeX}} 2006: Proceedings of the $16^{th}$ Annual
             Meeting of the European {\TeX} Users,
             {Debrecen}, {Hungary}},
  YEAR = {2006},
  MONTH = JUL,
  PAGE = {--},
  ISBN = {---},
  PS = {publish/eurotex2006.ps.gz},
  PDF = {publish/eurotex2006.pdf},
  URL = {http://www.matexhu.org/eurotex2006/},
  ABSTRACT = {}
}

@INPROCEEDINGS{fahmy:2006:qttat,
  AUTHOR = {Hossam A. H. Fahmy},
  TITLE = {{AlQalam for typesetting traditional Arabic texts}},
  BOOKTITLE = {The Annual Meeting of the International {\TeX} Users 
               Group, {Marrakesh}, {Morocco}},
  YEAR = {2006},
  MONTH = NOV,
  PAGE = {--},
  ISBN = {---},
  PS = {publish/qttat.ps.gz},
  PDF = {publish/qttat.pdf},
  URL = {http://www.tug.org/tug2006/},
  ABSTRACT = {}
}

@INPROCEEDINGS{fahmy:2007:srd,
  AUTHOR = {Sherif A. Tawfik and Hossam A. H. Fahmy},
  TITLE = {{Square Root and Division: An Improved Algorithm and 
            Implementation}},
  BOOKTITLE = {To be published},
  YEAR = {2007},
  MONTH = JUL,
  PAGE = {--},
  ISBN = {---},
  PS = {publish/srdai.ps.gz},
  PDF = {publish/srdai.pdf},
  URL = {},
  ABSTRACT = {  This paper develops an efficient algorithm for the
  computation of the square root operation. We propose a high order
  Newton-Raphson algorithm for the computation of the square root
  reciprocal. We also propose a more accurate algorithmic error
  analysis for the initial approximation algorithm.
  The double precision result is correctly rounded and we present an
  error analysis for the algorithm.

  The similarity between the multiplicative algorithms for the square
  root and the divison allows the integration of the two operations
  in a single unit. Our architecture uses a fused
  multiply add unit (FMA) and implements the four IEEE rounding modes.
  A VHDL model of the square root algorithm passes successfully a 
  functional testing composed of two million random test vectors.}
}


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