Wave Pipeline Designer

This tool demonstrates the benefit of wave pipelining for pipelined processor design. In a traditional pipeline, data must propagate from the input register of the longest stage through the combinational logic to the output register and be latched before the subsequent clock cycle. In a wave pipeline, new data is applied to the pipeline stage as soon as it can be guaranteed that under no circumstances will the new computation interfere with the current computation at any location in the pipeline stage

Input Value(s):

max circuit delay	Pmax =	ns
min circuit delay	Pmin =	ns
register clock to output	tco =	ns
output rise, fall time	trf =	ns
register setup time	tsu =	ns
register hold time	th =	ns
unintentional clock skew	tskew =	ns

Result(s):

Traditional Pipe Min Clock Period	Tclk_trad =	ns
Wave Pipe Min Clock Period	Tclk_wave =	ns
Max number of waves, Max Speedup	N =	waves

The clock period of the wave pipeline is determined by the variation in propagation delay of the combinational logic and the overhead associated with the input and output registers. This clock period is generally less than can be achieved with traditional pipelining, where the clock period is determined by the maximum propagation delay of the longest pipeline stage and the overhead of the registers. Noninteger numbers of waves require an intentional skew of the output clock with respect to the input clock.

Last update: 10/20/2001