This page lets you design the quotient-digit selection logic for your very own SRT floating-point divider. This is the type of divider that is inside the Intel Pentium and caused such controversy last year. For more information about the theory of SRT division, you can read a survey that summarizes SRT and other division algorithms. For more information about the complexity of SRT tables and the type of analysis that can be performed using the tools on this web-page, you can read the corresponding technical paper.

You enter the radix of the divider, the maximum allowable quotient digit, the number of bits in the residual and divisor estimates, and the truncation error in the residual estimate. This page will then tell you whether such a divider is possible or not. If it is, it will return the Gray-coded PLA entries corresponding to the quotient digit selection table. The Gray encoding allows for the optimal selection of quotient digits to minimize the complexity of the tables.

The output forms include the raw PLA, a minimized PLA using Espresso, or an equation form of the PLA using Espresso. The table input is in terms of p0, p1, p2, ... and d0, d1, d2, ... The highest weight is assigned to the lowest index, such that d0 is the most significant fractional divisor bit, and p0 is the most significant non-sign partial remainder bit.