List of NSF-Supported (SNAP) Publications
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- G. Bewick, P. Song, G. De Micheli and M. Flynn,
``Approaching a Nanosecond: A 32 Bit Adder,''
ICCD, Proceedings of the International Conference on Circuit and
Computer Design, Rye, NY, pp. 221-226, October 1988.
- C. Chao, Multiport Memory Design for an MCM Coprocessor,
Ph.D. thesis, Stanford University, December 1994.
- C. Chao and B. Wooley, ``A 1.3-ns, 32-Word by 32-Bit Three-Port
BiCMOS Register File,''Proceedings of the 1994 Bipolar/BiCMOS Circuits
and Technology Meeting, pp. 91-94, October 1994.
- C. Chao, K. Miyamoto, K. Sakui, W. Cheng, and B. Wooley, ``An Active
Substrate MCM System,''1994 Symposium on VLSI Circuits Digest of
Technical Papers, pp. 47-48, June 1994.
- W. Cheng, M. Beiley and S. Wong. ``Membrane Multi-Chip
Module Technology on Silicon,'' to be presented at IEEE
Multi-Chip-Module Conference, Santa Cruz, March 1993.
- F. Klass. Balancing Circuits for Wave Pipelining.
Technical report CSL-TR-92-549, October 1992.
- B. W. Langley and R. F. W. Pease.
``Superconducting Interconnects
for VLSI Multi-chip System Integration.''
In Proceedings, Symposium on VLSI Technology,
June 1990.
- J. M. Mulder, Nhon T. Quach, and Michael J. Flynn.
``An area model for on-chip memories and its application.''
Journal of Solid State Circuits, 26(2), February 1991.
- R. F. W. Pease.
``System Level Packaging: An Alternative to Monolithic ULSI.''
Invited Plenary Paper,
International Electron Devices Meeting,
December 1990.
- N. T. Quach and M. J. Flynn.
High-Speed Addition in CMOS.
Technical report CSL-TR-90-415, February, 1990.
- N. T. Quach and M. J. Flynn.
An Improved Algorithm for High-Speed Floating-Point Addition.
Technical Report CSL-TR-90-442, August, 1990.
- N. T. Quach, N. Takagi, and M. J. Flynn.
On fast IEEE rounding.
Technical Report CSL-TR-91-459, Stanford University, January 1991.
- N. T. Quach and M. J. Flynn.
Leading one prediction-implementation, generalization, and
application.
Technical Report CSL-TR-91-463, Stanford University, March 1991.
- N. T. Quach and M. J. Flynn.
Design and Implementation of the SNAP Floating-Point Adder.
Technical Report CSL-TR-91-501, December 1991.
- N. T. Quach and M. J. Flynn.
A Radix-64 Floating-Point Divider.
Technical report CSL-TR-92-529, June, 1992.
- Nhon Quach and M. J. Flynn.
``High-Speed Addition in CMOS.''
IEEE Transactions on Computers, Vol. 41, No. 12, December 1992.
- Nhon Quach. Performance Improvement in Basic Floating-Point
Operation. PhD thesis, Stanford University, 1993.
- E. M. Schwarz and M. J. Flynn.
``Cost-efficient high-radix division.''
Journal of VLSI Signal Processing, August 1991.
- E. M. Schwarz and M. J. Flynn.
Direct combinatorial methods for approximating trigonometric functions.
Technical report CSL-TR-92-525, May 1992.
- E. M. Schwarz and M. J. Flynn.
``Approximating the sine function with combinational logic.''
In Proc. of 26th Asilomar Conf. on Signals, Systems, and Computers.
October 1992.
- E. M. Schwarz and M. J. Flynn.
Using a floating-point multiplier to sum signed Boolean elements.
Technical report CSL-TR-92-540, August 1992.
- E. M. Schwarz. High Radix Algorithms for High-Order Arithmetic
Operations. PhD thesis, Stanford University, January 1993.
- P. Song and G. De Micheli,
``Circuit and Architecture Trade-offs for High-Speed Multiplication,''
IEEE Journal on Solid State Circuits,
Vol. 26, No. 9, pp. 1184-1198, September 1991.
- Paul Song. New Circuits and Structures for Combinational
Multipliers, PhD thesis, Stanford University, March 1993.
- Naofumi Takagi.
A radix-4 modular multiplication hardware algorithm.
Technical Report CSL-TR-91-458, Stanford University, January 1991.
- D. Wong.
``A High-Speed Hardware Unit for a Subset of Logic Resolution.''
In Proceedings of MICRO-21, pp. 73-78, November 1988.
- D. Wong, G. De Micheli, and M. Flynn.
``Designing High-Performance Digital Circuits Using Wave Pipelining.''
In Proceedings of VLSI '89, pp. 241-252, August 1989.
- D. Wong, G. De Micheli, and M. Flynn.
``Inserting Active Delay Elements to Achieve Wave Pipelining.''
In Proceedings of ICCAD '89, pp. 270-273, November 1989.
- D. Wong and M. Flynn. ``Fast Division Using Accurate Quotient
Approximations to Reduce the Number of Iterations.'' In Proceedings of
the 10th IEEE Symposium on Computer Arithmetic, pp. 191-201, June 1991.
- D. Wong.
Techniques for Designing High-Performance Digital Circuits Using
Wave Pipelining. PhD thesis, Stanford University, August 1991.
- D. Wong, G. De Micheli, and M. Flynn. ``A Bipolar Population
Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency.''
In Proc. International Solid-State Circuits Conference,
pp. 56-57, February 1992.
- D. Wong, G. De Micheli, and M. Flynn. ``A Bipolar Population
Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency.''
Journal of Solid-State Circuits, Vol. 27, No. 5, pp. 745-753, May 1992.
- D. Wong and M. Flynn. ``Fast Division Using Accurate Quotient
Approximations to Reduce the Number of Iterations.''
IEEE Transactions on Computers, 41(8):981-995, August 1992.
- D. Wong, G. De Micheli and M. Flynn,
``Algorithms for Designing High-Performance Digital Circuits Using
Wave Pipelining,''
IEEE Transactions on CAD/ICAS, pp. 25-46, January 1993.
Next: References
Up: SUBNANOSECOND ARITHMETIC for 1990-1993
Previous: Superconducting Chip-to-chip Interconnects
Michael Flynn
Tue Dec 13 10:27:47 PST 1994