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\title{SUBNANOSECOND ARITHMETIC for 1990-1993}
\author{Michael J. Flynn \\ Giovanni DeMicheli \\ R. Fabian Pease \\
Bruce Wooley}

\date{May 1993}

\abstract{
The Stanford Nanosecond Arithmetic Project is targeted at realizing an
arithmetic processor with performance approximately an order of magnitude 
faster than currently avaiable technology. The realization of SNAP is
predicated on an interdisciplinary approach and effort spanning research
in algorithms, data representation, CAD, circuits and devices, and
packaging. SNAP is visualized as an arithmetic coprocessor implemented
on an active substrate containing several chips, each of which realize
a particular arithmetic function.  We have fabricated a number of
prototype die.
}

\makefront

SNAP---the Stanford subnanosecond arithmetic processor---is an 
interdisciplinary effort to develop theory, tools, and technology
realizing an arithmetic processor with execution rates under 1 ns.
During the course of our SNAP project, we have made significant 
progress toward accomplishing a gigaflop (a billion floating-point 
arithmetic operations per second) computing element.
This report is an extended abstract summarizing the SNAP results.

\begin{table}[p]	%\caption{} \label{status}
\vspace*{1.75in}
\hspace*{-1.5cm}

\setbox0=\vbox{ 
\begin{minipage}{7.5in} 

\centering {Table 1: SNAP Die Fab Status} \smallskip	

\bt{|l|l|l|l|l|}
\hline
Die	&Company*	&Technology	&Status	&Project\\
\hline
\hline
Integer adder	&Signetics	&ECL	&F.T.	&Measured 2ns 32-bit integer [P1]\\
F.P. adder ($53b$ IEEE)	&HP Research	&CMOS	&Sub.	&15ns latency [P11]\\
Multiplier (pp) slice	&Signetics	&BiCMOS	&F.T.	&Under 10ns pp tree only [P20]\\
Multiplier (pp) slice	&Signetics	&BiCMOS	&F.T.	&Under 7ns pp tree only [P20]\\
F.P. multiplier ($53b$ IEEE)	&Sun Micro.	&ECL	&Sub.
&Full FMPY in under 5ns \\
W.p.\ multiplier (pp) slice	&Signetics	&ECL	&F.T.
&3.8ns cycle time measured [P28]\\
W.p.\ multiplier $16\times 16b$	&HP**	&CMOS	&Sub.
&1.8ns cycle time simulated (CMOS)\\
Divider	&---%SMOS
					&CMOS	&NYS	&Still under study\\
\hline
\et

*\,\fns 
Company that sponsored die fab. 
All but one (**) were paid for by sponsor company.

Abbreviations: 
 F.T. = Fully tested \ Sub.\ = Submitted \ NYS = Not yet submitted\\
W.p. = wave pipelined, F.P. = floating-point
\end{minipage}
}

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\end{table}

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\bibliographystyle{plain}
\begin{thebibliography}{000}

\bibitem{LIN81}
H. Ling.  ``High-Speed Binary Adder.''
{\em IBM Journal of Research and Development},
Vol.\ 25, No.\ 2 and 3, pages 156--166, May 1981.

\bibitem{Far81} M. P. Farmwald. {\em On the Design of High-Performance Digital
Arithmetic Units}. PhD theses, Stanford University, August 1981.

\bibitem{San89} M. Santoro. {\em Design and Clocking of VLSI Multipliers}. 
PhD thesis, Stanford University, October 1989.

\bibitem{Mas89}  Akira Masaki.
``Electrical Resistance as a Limiting Factor for High Performance Computer
 Packaging.'' {\em IEEE Circuits and Devices Magazine} 5(22), 1989.

\bibitem{Lan93} B. W. Langley. 
{\em High-Temperature Superconducting Microstrip Lines: 
 Digital System Interconnect Applications and Magnetic Penetration Studies}
PhD Dissertation, Stanford University, in preparation (1993).

\end{thebibliography}


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