
%% ??? NO EXPLICIT REFERENCE TO NSF GRANT
\item G. Bewick, P. Song, G. De Micheli and M. Flynn, 			
``Approaching a Nanosecond: A 32 Bit Adder,''
{\it ICCD, Proceedings of the International Conference on Circuit and
Computer Design,} Rye, NY, pp.~221--226, October 1988.

\item W. Cheng, M. Beiley and S. Wong. ``Membrane Multi-Chip 
Module Technology on Silicon,'' to be presented at {\em IEEE 
Multi-Chip-Module Conference}, Santa Cruz, March 1993.

\item F. Klass. Balancing Circuits for Wave Pipelining. 
Technical report CSL-TR-92-549, October 1992.

\item B. W. Langley and R. F. W. Pease.
``Superconducting Interconnects
         for {VLSI} Multi-chip System Integration.''
	In {\em Proceedings, Symposium on VLSI Technology},
	June 1990.

\item J.~M. Mulder, Nhon~T. Quach, and Michael~J. Flynn.
``An area model for on-chip memories and its application.''
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\item R. F. W. Pease.
	``System Level Packaging: An Alternative to Monolithic {ULSI}.''
	Invited Plenary Paper,
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	December 1990.

\item N. T. Quach and M. J. Flynn.
High-Speed Addition in {CMOS}.
Technical report CSL-TR-90-415, February, 1990.

\item  N. T. Quach and M. J. Flynn.
An Improved Algorithm for High-Speed Floating-Point Addition.
Technical Report CSL-TR-90-442, August, 1990.

\item N.~T. Quach, N.~Takagi, and M.~J. Flynn.
 On fast {IEEE} rounding.
 Technical Report CSL-TR-91-459, Stanford University, January 1991.

\item N.~T. Quach and M.~J. Flynn.
 Leading one prediction---implementation, generalization, and
  application.
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\item N. T. Quach and M. J. Flynn.
Design and Implementation of the SNAP Floating-Point Adder.
Technical Report CSL-TR-91-501, December 1991.

\item N. T. Quach and M. J. Flynn.
A Radix-64 Floating-Point Divider.
Technical report CSL-TR-92-529, June, 1992.

\item Nhon Quach and M. J. Flynn.
``High-Speed Addition in {CMOS}.''
{\em IEEE Transactions on Computers}, Vol.\ 41, No.\ 12, December 1992.

\item  Nhon Quach. {\em Performance Improvement in Basic Floating-Point 
Operation}. PhD thesis, Stanford University, 1993.

\item E.~M. Schwarz and M.~J. Flynn.
``Cost-efficient high-radix division.''
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\item E. M. Schwarz and M. J. Flynn.
Direct combinatorial methods for approximating trigonometric functions.
Technical report CSL-TR-92-525, May 1992.

\item E. M. Schwarz and M. J. Flynn.
``Approximating the sine function with combinational logic.''
In {\em Proc. of 26th Asilomar Conf. on Signals, Systems, and Computers}.
October 1992.

\item E. M. Schwarz and M. J. Flynn.
Using a floating-point multiplier to sum signed Boolean elements.
Technical report CSL-TR-92-540,  August 1992.

\item E. M. Schwarz. {\em High Radix Algorithms for High-Order Arithmetic 
Operations}. PhD thesis, Stanford University, January 1993.

\item P. Song and G. De Micheli,
``Circuit and Architecture Trade-offs for High-Speed Multiplication,''
{\it IEEE Journal on Solid State Circuits},
Vol.\ 26, No.\ 9, pp.~1184--1198, September 1991.

\item Paul Song. {\it New Circuits and Structures for Combinational 
Multipliers}, PhD thesis, Stanford University, March 1993. 

\item Naofumi Takagi.
 A radix-4 modular multiplication hardware algorithm.
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\item D. Wong.
``A High-Speed Hardware Unit for a Subset of Logic Resolution.''
In {\em Proceedings of MICRO-21}, pp.~73--78, November 1988.

% ??? NO EXPLICIT REFERENCE TO NSF GRANT
\item D. Wong, G. De Micheli, and M. Flynn.
``Designing High-Performance Digital Circuits Using Wave Pipelining.''
In {\em Proceedings of VLSI '89}, pp.~241--252, August 1989.

% ??? NO EXPLICIT REFERENCE TO NSF GRANT
\item D. Wong, G. De Micheli, and M. Flynn.  
``Inserting Active Delay Elements to Achieve Wave Pipelining.''  
In {\em Proceedings of ICCAD '89}, pp.~270--273, November 1989.

\item D. Wong and M. Flynn.  ``Fast Division Using Accurate Quotient 
Approximations to Reduce the Number of Iterations.''  In {\em Proceedings of
the 10th IEEE Symposium on Computer Arithmetic}, pp.~191--201, June 1991.

\item D. Wong.
{\em Techniques for Designing High-Performance Digital Circuits Using 
Wave Pipelining}. PhD thesis, Stanford University, August 1991.

\item D. Wong, G. De Micheli, and M. Flynn.  ``A Bipolar Population
Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency.''
In {\em Proc.\ International Solid-State Circuits  Conference}, 
pp.~56--57, February 1992.

\item D. Wong, G. De Micheli, and M. Flynn.  ``A Bipolar Population
Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency.''
{\em Journal of Solid-State Circuits}, Vol.\ 27, No.\ 5, pp.~745--753, May 1992.

\item D. Wong and M. Flynn.  ``Fast Division Using Accurate Quotient 
Approximations to Reduce the Number of Iterations.'' 
{\em IEEE Transactions on Computers}, 41(8):981--995, August 1992.

\item D. Wong, G. De Micheli and M. Flynn,
``Algorithms for Designing High-Performance Digital Circuits Using
Wave Pipelining,''
{\it IEEE Transactions on CAD/ICAS}, pp.~25--46, January 1993.
