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\begin{document}
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\title{\Large\bf The SNAP Project: Towards Sub-Nanosecond Arithmetic}
\author{Michael J. Flynn, Stuart Oberman, Steve Fu, Hesham Altwaijry, \\
Kevin Nowka, Gary Bewick, Eric Schwarz, and Nhon Quach \\
\\
Computer Systems Laboratory \\
Stanford University \\
Stanford, CA~~94305}
 
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\subsection*{\centering Abstract}
%IEEE allows italicized abstract
{\em
SNAP --- the Stanford subnanosecond arithmetic processor ---
is an interdisciplinary effort to develop theory, tools, and technology
for realizing an arithmetic processor with execution rates under 1 ns.
Specific improvements in clocking methods, floating-point
addition algorithms, floating-point multiplication algorithms, 
division and higher-level function algorithms, design tools, and
packaging technology were studied. These improvements have been
demonstrated in the implementation of several VLSI designs.

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}
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\section{Background}

%SNAP --- the Stanford subnanosecond arithmetic processor ---
%is an interdisciplinary effort to develop theory, tools, and technology
%realizing an arithmetic processor with execution rates under 1 ns.
%During the course of the SNAP project, we have made significant 
%progress toward accomplishing a gigaflop (a billion floating-point 
%arithmetic operations per second) computing element.

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Arithmetic operations including both integer and floating point add,
subtract, multiply, and divide form the basic building blocks of scientific
computation and signal processing.  Yet usually the optimization of their
performance is relegated to design exercises in which the building
blocks, the circuits/package/technology have been predefined and only the
algorithm itself and its implementation can be altered to achieve performance.

The Stanford subnanosecond arithmetic processor (SNAP) research
effort has targeted the full spectrum of tradeoffs, from devices,
materials, interconnections and circuits to algorithms and organization.
The SNAP project has made significant progress toward the development of
a gigaflop computing element.



%\begin{table}[p]        %\caption{} \label{status}
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\centering {{\small Table 1: SNAP Die Fab Status}} \smallskip    

\bt{|l|l|l|l|l|}
\hline
Die     &Company*       &Technology &Status &Result\\
\hline
\hline
Integer adder   &Signetics      &ECL    &F.T.   &2ns 32-bit integer [P4]\\
F.P. adder ($64b$ IEEE) &HP Research    &CMOS   &I.T.   &15ns latency [P18]\\
Multiplier (pp) slice   &Signetics      &BiCMOS &F.T.   &Under 10ns pp tree only [P24]\\
Multiplier (pp) slice   &Signetics      &BiCMOS &F.T.   &Under 7ns pp tree only [P24]\\
F.P. multiplier ($53b$ IEEE)    &Sun Micro.     &ECL    &I.T.
&Full FMPY in 5ns \\
W.p.\ multiplier (pp) slice     &Signetics      &ECL    &F.T.
&3.8ns cycle time [P29]\\
W.p.\ multiplier $16\times 16b$ &NSF   &CMOS   &F.T.
&3.3ns cycle time [P8] \\
W.p.\ vector unit ($16b$) &NSF   &CMOS   &F.T.  &3.3ns cycle time \\
Divider &---%SMOS
                                        &CMOS   &NYS    &Still under study\\
\hline
\et

*\,\fns 
Company or organization that sponsored die fab. 
%All but one (**) were paid for by sponsor company.

Abbreviations: 
 F.T. = Fully tested \ I.T.\ = Incompletely tested due to fab difficulties \ NYS = Not yet submitted\\
W.p. = wave pipelined, F.P. = floating-point
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\end{table*}

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%\bibliographystyle{plain}
%\begin{thebibliography}{000}

\bibitem{LIN81}
H. Ling.  ``High-Speed Binary Adder.''
{\em IBM Journal of Research and Development},
Vol.\ 25, No.\ 2 and 3, pp. 156--166, May 1981.

\bibitem{Far81} M. P. Farmwald. {\em On the Design of High-Performance Digital
Arithmetic Units}. PhD theses, Stanford University, August 1981.

\bibitem{mand} D. M. Mandelbaum. ``A Method for Calculation of the Square Root
Using Combinatorial Logic,'' {\em Journal of VLSI Signal Processing}, December 1993,
pp. 233-242.

%\bibitem{San89} M. Santoro. {\em Design and Clocking of VLSI Multipliers}. 
%PhD thesis, Stanford University, October 1989.
%
%\bibitem{Mas89}  Akira Masaki.
%``Electrical Resistance as a Limiting Factor for High Performance Computer
 %Packaging.'' {\em IEEE Circuits and Devices Magazine} 5(22), 1989.
%
%\bibitem{Lan93} B. W. Langley. 
%{\em High-Temperature Superconducting Microstrip Lines: 
 %Digital System Interconnect Applications and Magnetic Penetration Studies}
%PhD Dissertation, Stanford University, 1993.

\end{thebibliography}


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