\item H. Altwaijry and M. Flynn. Performance/Area Tradeoffs in Booth
Multipliers.
Technical report CSL-TR-95-684, Stanford University, November 1995.

\item G. Bewick.
{\em Fast Multiplication: Algorithms and Implementation}.
PhD thesis, Stanford University, 1994.

\item G. Bewick and M. Flynn. Binary Multiplication Using Partially
Redundant Multiples.
Technical report CSL-TR-92-528, Stanford University, June 1992.

%% ??? NO EXPLICIT REFERENCE TO NSF GRANT
\item G. Bewick, P. Song, G. De Micheli and M. Flynn, 			
``Approaching a Nanosecond: A 32 Bit Adder,''
{\it ICCD, Proceedings of the International Conference on Circuit and
Computer Design,} Rye, NY, pp.~221--226, October 1988.

\item W. Cheng, M. Beiley and S. Wong. ``Membrane Multi-Chip 
Module Technology on Silicon,'' {\em IEEE 
Multi-Chip-Module Conference}, Santa Cruz, March 1993.

\item S. Fu, N.~Quach, and M.~Flynn. 
Architecture Evaluator's Work Bench and Its Application to
Microprocessor Floating Point Units.
Technical report CSL-TR-95-668, Stanford University, June 1995.

\item F. Klass. Balancing Circuits for Wave Pipelining. 
Technical report CSL-TR-92-549, Stanford University, October 1992.

\item E. F. Klass.  {\em Wave Pipelining: Theoretical and
Practical Issues in CMOS}. PhD. thesis, Dept. of Elect. Engr.,
Delft Univ. of Technology, 1994.

\item K. Nowka and M. Flynn.
Environmental Limits on the Performance of CMOS Wave-Pipelined
Circuits.
Technical Report CSL-TR-94-600, Stanford Univ., Jan. 1994.

\item S. F. Oberman and M. J. Flynn.
An Analysis of Division Algorithms and Implementations.
Technical report CSL-TR-95-675, Stanford University, July 1995.

\item S. F. Oberman and M. J. Flynn,
``Implementing Division and Other Floating-Point Operations: A System 
Perspective,''
{\em Proceedings of SCAN-95, International Symposium on Scientific
Computing, Computer Arithmetic, and Validated Numerics}, pp. 18--24,
September 1995.

\item S. F. Oberman and M. J. Flynn.
Measuring the Complexity of SRT Tables.
Technical report CSL-TR-95-679, Stanford University, November 1995.

\item S. F. Oberman and M. J. Flynn,
``Reducing Division Latency with Reciprocal Caches,''
{\em Journal of Reliable Computing}, 2(2):147--153, April 1996. 

\item S. F. Oberman and M. J. Flynn,
``A Variable Latency Pipelined Floating-Point Adder,''
to appear in {\em Proceedings of Euro-Par'96}, August 1996.

\item S. F. Oberman and M. J. Flynn,
``Design Issues in Division and Other Floating-Point Operations,''
in press {\em IEEE Transactions on Computers}, 1996. 

\item N. T. Quach and M. J. Flynn.
High-Speed Addition in {CMOS}.
Technical report CSL-TR-90-415, Stanford University, February 1990.

\item  N. T. Quach and M. J. Flynn.
An Improved Algorithm for High-Speed Floating-Point Addition.
Technical Report CSL-TR-90-442, Stanford University, August 1990.

\item N. T. Quach and M. J. Flynn.
Design and Implementation of the SNAP Floating-Point Adder.
Technical Report CSL-TR-91-501, Stanford University, December 1991.

\item N. T. Quach and M. J. Flynn.
A Radix-64 Floating-Point Divider.
Technical report CSL-TR-92-529, Stanford University, June 1992.

\item N. Quach and M. J. Flynn,
``High-Speed Addition in {CMOS},''
{\em IEEE Transactions on Computers}, Vol.\ 41, No.\ 12, December 1992.

\item  N. Quach. {\em Reducing the Latency of Floating-Point 
Arithmetic Operations}. PhD thesis, Stanford University, 1993.

\item E. Schwarz and M. Flynn.
Using a floating-point multiplier to sum signed Boolean elements.
Technical report CSL-TR-92-540, Stanford University, August 1992.

\item E. M. Schwarz. {\em High Radix Algorithms for High-Order Arithmetic 
Operations}. PhD thesis, Stanford University, January 1993.

\item P. Song and G. De Micheli,
``Circuit and Architecture Trade-offs for High-Speed Multiplication,''
{\it IEEE Journal on Solid State Circuits},
Vol.\ 26, No.\ 9, pp.~1184--1198, September 1991.

\item D. Wong, G. De Micheli, and M. Flynn,
``Designing High-Performance Digital Circuits Using Wave Pipelining,''
{\em Proceedings of VLSI '89}, pp.~241--252, August 1989.

% ??? NO EXPLICIT REFERENCE TO NSF GRANT
\item D. Wong, G. De Micheli, and M. Flynn,  
``Inserting Active Delay Elements to Achieve Wave Pipelining,''  
{\em Proceedings of ICCAD '89}, pp.~270--273, November 1989.

\item D. Wong and M. Flynn, ``Fast Division Using Accurate Quotient 
Approximations to Reduce the Number of Iterations,''  {\em Proceedings of
the IEEE Symposium on Computer Arithmetic}, pp.~191--201, June 1991.
\vspace{1.4mm}

\item D. Wong. 
{\em Techniques for Designing  High- \linebreak Performance Digital Circuits Using Wave \linebreak Pipelining}. PhD thesis, Stanford University, August 1991.
\vspace{1.4mm}

\item D. Wong, G. De Micheli, and M. Flynn, ``A Bipolar Population
Counter Using Wave Pipelining to Achieve 2.5x Normal Clock Frequency,''
{\em Journal of Solid-State Circuits}, Vol.\ 27, No.\ 5, pp.~745--753, May 1992.
\vspace{1.4mm}

\item D. Wong and M. Flynn, ``Fast Division Using Accurate Quotient 
Approximations to Reduce the Number of Iterations,'' 
{\em IEEE Transactions on Computers}, 41(8):981--995, August 1992.

\newpage
\item D. Wong, G. De Micheli and M. Flynn,
``Algorithms for Designing High-Performance Digital Circuits Using
Wave Pipelining,''
{\it IEEE Transactions on CAD/ICAS}, pp.~25--46, January 1993.

