Brian Bray

We have continued our basic studies on special-purpose processors for pattern recognition and pattern perception.

Evaluating the usefulness of architectural/design decisions is complicated by the interdependence of architectural features, various levels of compiler sophistication, and the validity of benchmarks. At Stanford University, the Computer Architect's Workbench (AWB) has been developed to aid in evaluating designs. The Architect's Workbench is a set of tools to predict the relative performance of alternative computer and system architecture features. The Architect's Workbench runs actual programs for various hardware configurations.

The Architect's Workbench predicts the relative performance of alternative computer and system architectures. The system allows high-level tradeoff, including instruction format selection, instruction encoding, register set size and organization, and cache size and organization. The Compiler tools consists of compiler front ends, code optimizers, and register allocators. The remainder of the tools are used to simulate the architectures being studied. These consist of programs to do static analysis of the instruction and data stream and programs to simulate the memory hierarchy, i.e., instruction and data caches. Since simulation speed is crucial to examining many alternatives, the tools rely heavily on static analysis of the application to reduce simulation time.

As the issue rate of processors increases (from superscalar and/or superpipeline organizations), the demand on the memory system also increases. We have been extending the Architect's Workbench by developing new tools to further analyze the nature of access and use of memory. In this last year, with the use of these tools we have made several discoveries that can help optimize pipelined processors for memory access management.

• We have developed a two-level windowed register file to reduce the cycle time of to that of a smaller windowed register file while retaining the performance of a large windowed register file [5].

• We have developed a tag cache to eliminate the need to check the data cache before a perform write [6].

• We have developed subword caching to eliminate the need for subword access hardware being in the primary cache access path [2].

• We have developed translation hint buffers to eliminate the latency of address translation for a physically addressed instruction cache [3], [4].

• We have continued to explored page coloring; a simple modification to an operating system's page allocation algorithm to give physically addressed caches the access speed of virtually addressed caches [15].

In addition to our own research, we have continued to distribute the Architect's Workbench to other universities. We also have ported the AWB to the Sun4.