Date:     April 29, 1994

Time:     11:00 - 12:00 noon

Location: ERL 401


      WAVE-PIPELINING:  A NEW OBJECTIVE IN HIGH-PERFORMANCE CMOS DESIGN?

                           Wayne Burleson
            Department of Electrical and Computer Engineering
             University of Massachusetts, Amherst, MA 01003


                             ABSTRACT

We are currently exploring the potential of wave-pipelining concepts in
highly pipelined DSP circuits.   We have demonstrated and analyzed
wave-pipelining of dynamic logic, explored wave-pipelining as an
objective for modern logic synthesis tools, and studied the use and
impact of wave-pipelined circuits on higher-level systems.  We have
designed, fabricated and tested several wave-pipelined CMOS chips.

In this talk, I will summarize our results and draw conclusions about
the benefits, pitfalls and future of wave-pipelining as a timing method.
I will conclude by posing some open research questions which arise in
the design, verification and test of wave-pipelining but have much wider
impact on other aggressively timed circuits.

This is joint work with M. Ciesielski and is supported by the National
Science Foundation under grant MIP-9208687.


                               BIO

Wayne Burleson has been exploring the area of VLSI Signal Processing
for 11 years.   His work has included research, development, teaching and
industrial work at a variety of levels including algorithms, architectures,
circuits and CAD tools.   Dr. Burleson is currently an Assistant Professor
of Electrical and Computer Engineering at the University of Massachusetts
at Amherst.  He received his BSEE and MSEE from MIT in 1983 and his PhD in
VLSI Signal Processing from the University of Colorado, 1989. He worked as
a custom DSP chip designer for 4 years at VLSI Technology Inc. and
Fairchild Semiconductor.