Parameterized Convolution Filtering in an FPGA

Richard Shoup - Interval Research, Palo Alto,

This talk discusses the simple idea of parameterized program generation of convolution filters in an FPGA. Applications in image processing include real-time video and desktop publishing. An example 2-D filter pipeline is assembled from a set of multipliers and adders, which are in turn generated from a canonical serial-parallel multiplier stage. The real purpose of this talk, however, is to disparage the state of today's tools for FPGA design, and to offer some suggestions from modern software development tools and languages.