A Variable Latency Pipelined Floating-Point Adder

                               Stuart Oberman



  Addition  is   the  most  frequent  floating-point  operation  in   modern
microprocessors.     Due  to  its  complex  shift-add-shift-round  dataflow,
floating-point  addition   can  have   a  latency   larger  than   that   of
multiplication.  To achieve maximum  system performance, it is necessary  to
design the FP adder to have  minimum latency, while still providing  maximum
throughput.

  This  talk  presents  a  new  variable  latency   FP  addition  algorithm.
Previous research has demonstrated techniques to reduce the minimum  latency
of the FP  adder by  pre-computing several  results and  selecting the  true
result from these.  The variable latency addition algorithm to be  presented
exploits the behavior of dynamically-scheduled processors which can  utilize
functional units  that complete  in variable  time.   Simulation  on  SPECfp
applications demonstrates that  an average  speedup in  addition latency  of
up to  1.33  is  possible using  this  algorithm,  while  still  maintaining
single-cycle throughput.