Subject: Tadao Nakamura, THE SHIFT MACHINE, and MISD Architectures

    Summer Session: Computer Architecture and Emulation Seminar

http://arith.stanford.edu/courses.html
http://arith.stanford.edu/ee385b_sched.html
http://arith.stanford.edu/abstracts/nakamura_21jun95

                      Usual Time and Place:
            Wednesday, June 21, 12:15-13:15, ERL 401

             Title: Introduction to THE SHIFT MACHINE
             ---From Exploiting MISD Architectures---

        Spearker: Tadao Nakamura, nakamura@arith.stanford.edu
       Visiting Professor from Tohoku University  (Sendai, Japan)

ABSTRACT

To date, MISD architectures have not been deeply exploited.   In 
comparison with SISD, SIMD, and MIMD architectures, MISD seems to have 
unrevealed but outstanding features for data/information processing.   
CPU speeds are increasing much faster than memory access times.   In 
this talk, the beneficial aspects of these trends might appear by taking 
another look at MISD.   Latencies in memories systems are considered a 
serious problem, but by introducing an alternative structure, these time 
delays can be welcomed in high speed processing.   Our design, called 
the SHIFT MACHINE, is composed of an array of sift registers each 
connected with a corresponding array of ALUs.   In contrast with the 
SISD, SIMD, and MIMD processing schemes, data (as opposed to centralized 
control) is the leading part in data/information processing environments 
on MISD architecture.   In this talk, the fundamentals of MISD 
architecture are described and then the future direction of expandable 
functions of MISD will be forecasted or inferred.