EE385B seminar
Gates, room 100
November 18, 12:15 PM
 
 
CLOCKING METHODS FOR MODERN PROCESSORS AND PIPELINES
Albert Liddicoat
 
The increase in clock frequency, die area, and the number
of transistors per die is driving the clock overhead to be 
an increased percent of clock cycle time.  Traditional 
sequential design methodologies have inherent overhead from
storage element delay, clock skew, clock cycle partitioning, 
and are designed for worst case timing constraints.  We will 
discuss alternate design techniques including micropipelines,
self-timed circuits, wave pipelining, and skew-tolerant 
domino circuits and analyze these techniques with respect to
clocking overhead.