Hyuk-Jun Lee
21 October 1998

Topic: Designing a Partitionable Multiplier
 
This report presents the design of a 64-bit integer multiplier core
that can perform two 32-bit or four 16-bit integer multiplications and 
additions. The proposed multiplier removes sign and constant bits from 
its core and projects them to the boundaries to minimize the complexity 
of base cells.  It also adopts an array-of-arrays architecture with unequal
array sizes by decoupling partial product generation from carry save
addition.  This makes it possible to achieve high speed for 64-bit
multiplication.  The design, which was done in dual-rail domino, is
tested for functionality in Verilog and simulated in HSPICE for a
0.35 um process. The estimated delay excluding a final adder is
4.49 ns at 3.3V supply and 25c.  The estimated area is 5.2 mm^2.