Special University Oral Examination

            Architecture and Computer Aided Design Tools for A
                   Field Programmable Multi-chip System

                               Sanko Lan
                     Information Systems Laboratory
                    Department of Electrical Engineering
                           Stanford University

                       10:00 am  Wednesday, May 31
                             McCullough  240


                                Abstract

A Field Programmable Multi-chip System (FPMCS) can be used to emulate
or prototype a digital system, such as a microprocessor, before it is
integrated on a chip so that thorough functional verification and early
software development may be performed.  An FPMCS consists of electrically
configurable chips, such as FPGAs and FPICs, connected via a fixed wiring
network.  The logic density and performance of an FPMCS are determined by
the choice of the configurable chips, how they are interconnected,
the choice of the packaging  technology, and the configuration software.
Existing FPMCSs use off the shelf configurable chips mounted on printed
circuits boards (PCBs).  Such systems suffer from low logic density and
performance.

In the talk, we present a new reprogrammable interconnect architecture
for FPMCS.  Each configurable chip on the FPMCS consists of an FPGA logic
core surrounded by a configurable interconnection frame.  The chips are
mounted on a deposited MCM substrate and interconnected via a regular
fixed wiring network.  Interchip communication is done by configuring
the interconnection frame.  We describe the placement and routing tools
we developed for mapping designs onto the FPMCS.  The placement phase is
divided into partitioning, chip assignment, and iterative improvement
steps.  The routing phase is divided into global routing, channel routing
and track assignment steps.  Channel routing involves new NP-complete
problems denoted by Exact Segmented Channel Routing and K-wire Exact
Segmented Channel Routing.  We show how the tools are used to
optimize the architecture of the FPMCS.

Experimental results show that our FPMCS achieves one to two orders of
magnitude higher logic density and over a factor of two higher
performance than existing FPMCSs which are implemented using PCBs.
Assuming the same process technology, the same configurable logic
architecture and the same MCM technology we show that our FPMCS
architecture still achieves higher logic density and performance than
other FPMCS architectures.

      Refreshments will be served at 9:45am in McCullough 240