EE385b Seminar, May 21, 1997, 12:15 (noon), Gates B08.

       EE385b Computer Architecture Seminar

http://arith.stanford.edu/ee385b_sched.spr97.html

Title:  Nic -- A Compiled Simulator Generator
Speaker:   John Johnson, Micro Magic, Inc., jdj@arith.stanford.edu
Date:   May 21, 1997, 12:15 (noon)
Place:    CS Building, Gates B08.

Abstract:

  Processor verification requires many levels of simulation and huge
amounts of CPU time.  In this talk I'll present a strategy for
simulating the large number of cycles required to verify the logic
behavioral model of a processor.  This strategy is translating the
Verilog description of an edge-trigger register based processor design
into a C program, thereby creating a high performance cycle based
simulator.

  I'll present an overview and some internal details of Nic, a program I
have written for translating a subset of Verilog into C.  A Nic
created functional simulator achieves about a 300 times speed
improvement over the Verilog simulation.  This performance improvement
is possible because the register based design style allows efficient
static ordered gate evaluation.