Latency Tolerance for Dynamic Processors Jim Bennett Various hardware schemes have been proposed for improving the latency tolerance of processors, such as stream buffers and stride prediction tables. The studies that have been done on these techniques to date have all involved static processors. Since dynamically scheduled processors are now being produced by most major microprocessor vendors (i.e. Intel, HP, IBM, Sun, and MIPS), it is interesting to look at whether these techniques might be effective for dynamically scheduled processors. In this talk, I describe these schemes, and show that they are generally ineffective for dynamically scheduled processors. I discuss some of the reasons for this, and describe a new technique, load address correlation, that shows some promise for improving the latency tolerance of dynamically scheduled processors.