Patrick Hung November 4, 1998 Stochastic Congestion Model for VLSI Systems Designing with deep submicron presents new challenges in complexity, performance, and productivity. As feature size decreases, global interconnect plays a dominant role in determining the chip performance. Interconnect congestion affects not only routability but also the area, performance, and power consumption of a chip. Traditionally, VLSI congestion is modeled by a rat's nest or similar connectivity visualizations. These techniques require human interaction to identify routing congestion. For speed and complexity reasons, they do not model via minimization, routing obstacles, multi-pin nets, and routing among macro blocks. As chips become more complicated, these techniques appear to be insufficient. In this seminar, we will present a genearlized stochastic congestion model which includes via minimization, routing obstacles, multi-pin nets, and routing among multiple macro blocks. Based on the congestion model, we have derived the objective functions to optimize global interconnect delay and power consumption. We have implemented an interactive floorplanner (IPlan) which calculates the routing congestion. We will present and discuss some results in this seminar.