The register file is a critical part of a microprocessor. Its access time can impact cycle time and processor performance. Recent superscalar processors issue four instructions per cycle and this trend is increasing.
Based on the register file timing model developed by Norman Jouppi and the feature size scaling model developed by Grant McFarland, we will investiage tradeoffs between register access time and the number of ports for various features sizes. We will also look at some architectural ideas to speed up register file access time.