EE385B Computer Architecture and Emulation Seminar A Self-Clocked FPGA for Functional Simulation and Logic Emulation Dana How Information Systems Laboratory Department of Electrical Engineering Stanford University Wednesday, May 31, 12:00 pm ERL 401 Abstract Before Field Programmable Gate Arrays were developed, the lengthy fabrication delays and large one-time costs associated with gate arrays and semicustom design were seen as the major impediment to exploratory design. Although the many FPGA architectures introduced over the last decade have succeeded in eliminating these obstacles, these architectures and their supporting CAD tools still do not fully support exploratory design: typically the CAD tools take far too long to map a design into a larger FPGA, or to partition and map the design into several FPGAs, for the logic designer to enjoy the interactive design process familiar to users of integrated software compiling and debugging systems. In this talk, we present a new FPGA more amenable to exploratory design. This FPGA features (1) SRAM programmability to support rapid reprogram- mability, (2) regular segmented routing channels more easily and rapidly routed by CAD tools than the interconnect architectures seen in commercial SRAM-based products and (3) a self-clocked architecture which eliminates clock distribution problems and facilitates the composition of multiple FPGAs. Although each of these features in isolation imposes a notable area penalty, we argue that their combination results in an improvement in flexibility, usability and performance at an acceptable cost in area for rapid proto- typing, compared to other architectures. We will present an overview of eight separate FPGA designs incorporating these ideas, focusing on four submitted to MOSIS. The final chip is a complete FPGA comprising a 6x4 array of configurable logic modules, segmented routing channels, a configurable I/O ring and an integral controller for various programming, testing and single-step modes.