Multiplication is one of the basic arithmetic operations. In fact 8.72 % of all instructions in typical scientific programs are multiplies. Therefore, the speed of the multiplier is a critical issue in determining the performance of microprocessors. Recent advances in integrated circuit fabrication technology have resulted in both smaller feature sizes and larger die areas. Processor designers have recognized this and it has become common for modern microprocessor to have floating point multipliers implemented fully in hardware, in contrast to in software as in the previous generations. In fact the very latest processors also implement integer multiplication in hardware to speed up address translation, array indexing, and other integer operations.

This research addresses the issue of how to make best use of the silicon area available for building a multiplier. This talk begins by examining the tradeoff between the number of tracks/channel and the topology used in the design of the multiplier. We then show that an algorithmic approach to the design of the partial product reduction tree is superior than the regular hand-layouts.

Finally we will examined the technology scaling effects for multipliers, and we will show that wire capacitance will continue to dominate the extra latency due to wires.