Design of the Thinning Chip for Image Processing

                             Tackdon Han



In general, the recognition of the binary images can be divided into two steps
which are preprocessing and recognition. Before getting into recognition step,
the preprocessing step is usually required to get sufficient information to 
recognize the binary images.

A preprocessing is very important step, since it takes most of time in
the whole processing of recognition procedure.
Many researches have been done in designing of fast and
efficient preprocessing algorithm.
As part of the preprocessing, we study two modules which are noise elimination
and thinning of the binary images.

Noise elimination means removal of falsely placed pixels in original images.
With this step, the thinning job can be effictively and easily performed.
The thinning is a crucial process to provide a clear understanding of
a original binary image by skeletonizing the image.  

The most of the past work in preprocessing has been 
done through the software approach which results in very slow operation.
This slow operation is mainly due to many iterative operations with a heavy
access of memory. Even using a parallel computer leads to the limit of the speed
because of a heavy access of memory. In order to resolve this constraint, we 
design a ASIC (Application Specific Intergrated Circuit) chip to accelerate the
preprocessing step. We derive a hardware oriented thinning algorithm which 
requires a relatively few masks. The thinning chip has 1k SRAM inside and
32 masks can be carried out in parallel. In this talk, we present the
thinning and noise elimination algorithms with VHDL simulation result.