Recorded: December 2,1994. 74 minutes firstname.lastname@example.org
VirtualWires: A Technology for Massive Multi-FPGA Systems
Anant Agarwal, Virtual Machine Works, Inc.
Field-programmable gate arrays (FPGAs) are a fast growing technology that enable the implementation of teconfigurable logic systems. A mosaic of a few hundred FPGAs can implement customized computing platforms for many applications whose performance can outstrip even that of supercomputers. This lecture discusses a new compilation technology called VirtualWires, which uses a discrete timing algorithm and a multiplexing methodology to enable the construction of scalable and cost-effective multi-FPGA systems. This lecture overviews the fundamentals of FPGAs and the multi-FPGA opportunity, and presents the VirtualWires approach taking examples from logic emulation.
Anant Agarwal is chairman and chief scientist of Virtual Machine Works, Inc.
He is on leave from MIT where he is Associate Professor of Electrical Engineering and Computer Science and where he led the Alewife multiprocessor project. He holds a PhD in electrical engineering from Stanford University, specializing in computer architecture and VLSI.
* Babb, J.; Tessier, R.; and Agarwal, A. "VirtualWires: Overcoming Pin Limitations in FPGA-Based Logic Emulators." Proceedings . of the IEEE, Workshop on FPGAs for Custom Computing Machines, April 5-7, 1993, Napa, CA. Los Alamitos, CA: IEEE Computer Science Press.
Selvidge, C.; Agarwal, A.; Dahl, M.; and Babb, J. "TIERS: Topology Independent Pipelined Routing and Scheduling for . VirtualWires Compilation." Proceedings of the 1995 ACM . Third International Symposium on FPGAs, Feb.12-14.
* Thomas, D., and Moorby, P The Verilog Hardware Description Language. Boston, MA: Kluwer Academic Publishers, 1991.
* Trimberger, S. Field-Programmable Gate Array Technology. Boston, MA: Kluwer Academic Publishers, 1994.
* Proceedings of the IEEE, Workshop on FPGAs for Custom Computing Machines, April 5-7,1993, Napa, CA. Los Alamitos, CA: IEEE Computer Society Press.
* introductory reference
Summary of the discussion after the show:
The subject is presentend clearly, albeit a commercial streek is apparent.
The comment was made that the labels for "virtual clock" and "user clock" are misleading. Time-sharing hardware resources will clearly lead to a reduced clock rate (sub-sampling), this reduced rate would be more properly labeled "virtual clock".
A second comment was made, there clearly is a trade-off between (user) clock-rate and hardware resource usage, i.e. the user clock-rate is lower in general if more wires (or gates) are time-shared. There is no "free lunch" as the talk seems to suggest. In summary, time-sharing and replication of resources can be used to optimize the mapping onto FPGA's (not too surprisingly).