TITLE: High-Speed Flip-Flop Design

Speaker: Borivoje Nikolic
University of California, Davis, CA
Texas Instruments Storage Products Group, San Jose, CA

Flip-flops and latches are essential for the performance of high-speed
digital systems, because of tighter timing constraints and low power
requirements.  A comparison of recently published flip-flops is =
presented.
Sample master-slave latches and pulse-triggered latches are analyzed.
A new sense-amplifier-based flip-flop with improved second stage,
resulting in balanced differential output with improved driving ability
and a small setup time and delay is presented. The new design was
verified in a test chip, implemented in Leff =3D 0.18um CMOS technology,
exhibiting sum of setup time and clock to output delay of 170ps,
driving fanout of two.

Short speaker's bio:

Mr. Nikolic received his Dipl. Ing. and M.Sc.E.E. degrees from =
University
of Belgrade, Yugoslavia in 1992 and 1994 respectively.
Currently, he is finishing his Ph.D. degree studies at University
of California at Davis, while being with Texas Instruments Storage
Products Group, San Jose, CA.
His research interests include high-speed digital integrated circuits,
VLSI implementation of communications and signal processing systems
as well as analog circuit design.