Traditional top-down VLSI floorplanning methodology has major difficulties in deep-submicron designs. When the frequency surpasses a gigahertz and as many as a billion transistors on a single die, the top-down approach becomes very inefficient and ineffective.

In this talk, I will introduce a new floorplanning algorithm which takes advantage of early area, timing, and power estimation. The estimation is carried out using our proposed stochastic congestion model. To improve the area/time/power efficiency, our floorplanner is based on a flexible sequence-pair structure, and the optimization is done using using simulated annealing techniques.

Using MCNC test cases as our benchmark, I will present and discuss the area, power, and delay tradeoffs of our floorplanner.

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