"Automated Allocation of Complex Components"
Jim Smith

As the size of transistors shrinks according to Moore's Law, the
amount of functionality that can be put on a single die has grown
exponentially. However, since the advent of RTL based design, the
design methodologies and tools that support IC design have
struggled to keep up. This has resulted in a gap between what can
be designed in a single year and the total functionality that can
be implemented in an IC. One mechanism that promises to close this
gap is design reuse. 

In mapping high level specifications to reusable designs, the
functionality of the specification must be compared against that
of the existing design. This is complicated by the fact that the
existing design may described at low level, with constructs such
as bit level operators and registers.  We will demonstrate
algorithms that allow IP vendors to generate compact,
canonical, word-level representations for combinational and
sequential boolean logic. This allows arithmetic system 
specifications to mapped to existing implementations quickly and 
accurately.