R. Sudhakar on Wave Pipelining in YADD: A Novel Non-iterative Synthesis and Layout Technique Abstract With the continuous scaling of technology and deep-submicron CMOS design, we are facing the challenges of increased crosstalk effects and increased portions of delay caused by the interconnect. Since these routing wires take up a large portion of the layout area, and are difficult to estimate, they cause increased delay and area unpredictabilities. In this paper we present a new approach to synthesizing functions that avoids the normal iterations between synthesis, technology mapping and layout, which removes the interconnect and routes by abutment. Thus, we can have shorter and more predictable delays, and sometimes even layouts with reduced areas. Using this scheme we can achieve equal delays along different paths, which makes wave pipelining a reality, and hence we can clock these circuits at much higher frequencies, compared to what is possible in a conventionally designed circuit. In this paper, we propose the logic and layout synthesis schemes and algorithms, discuss the physical layout part of the process, and back up our scheme with simulation results.