Coarse grain carry architecture for FPGA Chuck H. Lee hyukjunl@arith.stanford.edu Computer Systems Laboratory Department of Electrical Engineering Stanford University Wednesday, Jan 20th, 12:15am FPGAs are emerging as a viable alternative to custom logic or DSP in the areas where throughput and energy efficiency are the major concern. In this talk, I will introduce the concept of throughput density which will be used as a metric to compare different FPGA architectures and its relation to energy-delay product. Then, I will continue by talking about the performance bottleneck of current architecture, especially the grain size. As a method to increase the grain size, new coarse grain architecture will be presented and its simulated performance over various applications will be discussed.