Computer Architecture: Pipelined and Parallel Processor Design

Michael J. Flynn

This text on computer design aims at leading the field away from the notion of computer design as an art form and establishing it as a science. Available and current data have been synthesized into a consistent package designed for advanced students and professionals in the field. The criteria in selecting data was to choose that which a prudent engineer would use in designing a new system. The text begins with the purpose of bringing the audience together into a common framework and use of terms. The first chapter introduces basic concepts, definitions, terms and notions in instruction sets and machines. From here, the text moves to include a detailed presentation of pipelined processor design, the effects of cache on processor performance, and the effects of memory design decisions on processor and cache configurations.

ISBN 0-86720-204-1, $71.25
Jones and Bartlett Publishers
1-800-832-0034

To purchase a copy, send e-mail to custserve@jbpub.com, and mention item code 204-1. Follow the link (book cover and title, above) to see J&B's cool lighthouse gif...

A postscript errata is now available. Also in .pdf. [NEW]

On-line Processor Design Tools are available to supplement exercises within the textbook.

For instructors, a partial solution set is available in PS or PDF formats. To receive authorization and the password, please contact Jones and Bartlett at 1-800-832-0034, or email our webmaster. These solutions are under development (usually revised each winter quarter).

Comments and corrections on the book or solution set are welcome; kindly send email to flynn@ee.stanford.edu.

Publisher comments to

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phone: 508-443-5000, fax: 508-443-8000, email: info@jbpub.com.

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